A NAND flash memory device that includes memory cells of a floating gate type having a gate electrode structure in which a floating electrode or gate (FG) and a control electrode or gate (CG) are laminated, is known. Recently, with advances in miniaturization and high integration of nonvolatile semiconductor storage devices, the gate length and the gate width of such memory cells have been reduced, so that the effect of capacitive coupling between adjacent memory cells is no longer negligible. As the interference effect between adjacent memory cells rises, there is an increase in the threshold voltage distribution of the memory cells to reduce the reliability of data stored in the memory cells.
Each memory cell of the floating gate type is provided with a floating electrode and a control electrode via a tunnel insulating film on a semiconductor substrate, and an interelectrode insulating film is formed between these electrodes. In addition, an element isolation region is formed between adjacent memory cells, and an element isolating-insulating film is embedded in the element isolation region, obtaining the necessary element characteristic.
A coupling ratio Cr, which is an index of the element characteristic, can be expressed by Cr=Cipd/(Cipd+Cox), and this coupling ratio can be improved by increasing the capacitance Cipd between the control electrode and the floating electrode or by decreasing the capacitance Cox between the semiconductor substrate and the floating electrode. At the side of the tunnel insulating film, an element isolating-insulating film is formed, and with the increase in the miniaturization of devices, the electric field through this element isolating-insulating film is no longer negligible, increasing the capacitance Cox. If the capacitance Cox increases, the coupling ratio decreases, causing a degrading of the write characteristic.
In addition, when the memory cells are set to a write nonselective state, a selective gate is turned off, setting the channel of the memory cells to a floating state. If the channel of the memory cells is in a floating state, the applied voltage of the control electrode is coupled, raising the channel potential. If the channel potential rises, in principle, the injection of electrons into the floating electrode is suppressed because of the shortage in the potential difference between the floating electrode and the channel. As a result, write processing cannot be implemented.
However, since the width of the element isolation region is reduced with the increase in density of the memory cells, the adjacent interference effect rises to increase the capacitance between the adjacent channels. As a result, if a write selective memory cell is adjacent to a write nonselective memory cell, the channel of the write selective memory cell is capacitively coupled with the channel of the write nonselective memory cell, so that no writing into the write selective memory cell may occur, or wrong writing into the write nonselective memory cell may occur.